Devices without current crowding effect at the finger&#39;s ends

ABSTRACT

ESD protection devices without current crowding effect at the finger&#39;s ends. It is applied under MM ESD stress in sub-quarter-micron CMOS technology. The ESD discharging current path in the MMOS or PMOS device structure is changed by the proposed new structures, therefore the MM ESD level of the NMOS and PMOS can be significantly improved. In this invention, 6 kinds of new structures are provided. The current crowding problem can be successfully solved, and have a higher MM ESD robustness. Moreover, these novel devices will not degrade the HBM ESD level and are widely used in ESD protection circuits.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. Utility applicationSer. No. 10/600,524, filed Jun. 23, 2003, which is hereby incorporatedherein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an ESD protection device andparticularly to an ESD protection device eliminating ESD currentcrowding events, so that a higher ESD level may be achieved under MM ESDtesting.

2. Description of the Prior Art:

ESD damage has become one of the main reliability concerns facing IC(integrated circuit) products. Particularly, when scaled down to thedeep sub-micron regime and the thinner gate oxide, the MOS become morevulnerable to ESD stress. For general industrial specifications, theinput and output pins of IC products must sustain HBM (Human-Body-Model)ESD stress of over 2000V and MM (Machine-Model) ESD stress of over 200V.Therefore, ESD protection circuits must be placed around the input andoutput (I/O) pads of the IC to protect IC against the ESD stress.

ESD protection devices are frequently drawn with large device dimensionsand realized by finger-type layout to save total layout area. The layouttop views and cross-sectional views of the prior arts to improve the ESDlevel of ESD protection devices by layout method are shown in FIGS. 1Aand 1B. It is formed on a P silicon substrate 11 and includes a STI(shallow trench isolation) 13 enclosing an active region 12, a P guardring 14 enclosing the STI 13, two gates 15, each composed of polysiliconlayer 151, gate oxide 152 and spacers 153, and N drain and source region161 and 162 placed in between and on the outer sides of the gates 15.The gates, source region, and body are typically connected to the groundwhile the drain region is connected to the input/output pad. Thefundamental theorem of ESD protection design is based on the mechanismsof the MOS and the parasitic lateral n-p-n bipolar (BJT) under highcurrent, and high field conduction. FIGS. 2A and 2B are sectional viewsand an equivalent circuit of a NMOS transistor, with the drain 22 as thecollector, substrate 21 as the body and source 23 as the emitter. DuringESD stress, high field at the drain causes the N+ to P substratejunction to enter an avalanche breakdown condition, generating excessiveelectron-hole pairs. The current of the electron-hole pairs forwardbiases the substrate-source (PN junction), and the voltage drop acrossthe substrate resistances increase the BE junction voltage of theparasitic BJT which is triggered to generate the snapback region in itsI-V curves, as shown in FIG. 3. Thus, the parasitic BJT turns on to andbypass the ESD current.

FIGS. 4A and 4B are top and sectional views of another conventional ESDprotection device, a gate grounded NMOS. With comparison to the ESDprotection device in FIGS. 1A and 1B, it is noted that the bullsubstrate resistance of the BB′ region is much larger than that of theAA′ region. This allows the parasitic BJT of the BB′ region to turn onfaster than that of the AA′ region with higher collector current tobypass the ESD current and spread through the BB′ region. The parasiticBJT of the BB′ region can provide larger effective area than the AA′region to discharge the ESD current, therefore it may have a high HBMESD robustness. However, under MM ESD zapping, the drain nodeconductivity with higher peak currents of 3˜4 Amps (for 200V MM ESDstress) often cause ESD damage at the corner or finger's end regions.The cause of damage is MM ESD current 3 or 4 times higher through anextremely small resistance than the HBM ESD current. Although theresistance of the AA′ region is smaller than that of the BB′ region, thebreakdown current (due to ESD zapping at the drain) of the drain tosubstrate junction at the AA′ region is still high enough to forwardbias and to turn on the parasitic BJT at the AA′ region, before turningon the parasitic BJT at the BB′ region. Thus, an excess of currentcrowds around the AA′ region and causes device failure at this region.Such damage is commonly shown in photographic training materials used inESD protection design training courses.

SUMMARY OF THE INVENTION

The object of the present invention is to provide an ESD protectiondevice eliminating ESD current crowding events to achieve a higher ESDlevel under MM ESD testing.

The present invention provides a first ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, a second gate disposed on a first side of the first gate andnear the first end of the first gate, and a first and second dopingregion on the first and a second side of the first gate, and coupled toa second and the first node respectively, wherein the first dopingregion has a first gap under the second gate.

The present invention provides a second ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, a second gate disposed on a second side of the first gateand near the first end of the first gate, and a first and second dopingregion on a first and the second side of the first gate, and coupled toa second and the first node respectively, wherein the second dopingregion has a first gap under the second gate.

The present invention provides a third ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, wherein the first doping region has a first gap nearthe first end of the first gate.

The present invention provides a fourth ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, wherein the second doping region has a first gap nearthe first end of the first gate.

The present invention provides a fifth ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, wherein the isolation region protruding into thefirst doping region near the first end of the first gate.

The present invention provides a sixth ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, wherein the isolation region protruding into thesecond doping region near the first end of the first gate.

The present invention provides a seventh ESD protection devicecomprising a substrate, an isolation region on the substrate, enclosingan active region, a first gate having a first and second end overlappingthe isolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, wherein the isolation region has a first portionunder the first end of the first gate protruding into both the first andsecond doping region.

The present invention provides an eighth ESD protection devicecomprising a substrate, an isolation region on the substrate, enclosingan active region, a first gate having a first and second end overlappingthe isolation region to stretch over the active region, and coupled to afirst node, a first and second doping region on the first and a secondside of the first gate, and coupled to a second and the first noderespectively, and a third doping region disposed under the first andsecond doping region and near the first end of the first gate, having adoping concentration lower than that of the first and second dopingregion.

The present invention provides a ninth ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, a first and second doping region on the first and a secondside of the first gate, and coupled to a second and the first noderespectively, and a first well disposed under the first doping regionand near the first end of the first gate.

The present invention provides a tenth ESD protection device comprisinga substrate, an isolation region on the substrate, enclosing an activeregion, a first gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to afirst node, and a first and second doping region on the first and asecond side of the first gate, and coupled to a second and the firstnode respectively, and wherein the first gate protruding into the firstdoping region so that, in the first doping region, a width of a centerportion is larger than those of portions near the first and second endof the first gate.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawings,given by way of illustration only and thus not intended to be limitativeof the present invention.

FIGS. 1A and 1B are top and sectional views of a conventional ESDprotection device.

FIGS. 2A and 2B are sectional views and an equivalent circuit of a NMOStransistor.

FIG. 3 is a diagram showing a relation between the current and breakdownvoltage of a NMOS transistor.

FIGS. 4A and 4B are top and sectional views of another conventional ESDprotection device.

FIGS. 5A and 5B are top and sectional views along a line AA′ of an ESDprotection device according to a first embodiment of the invention.

FIGS. 6A and 6B are top and sectional views along a line AA′ of an ESDprotection device according to a second embodiment of the invention.

FIGS. 7A and 7B are top and sectional views along a line AA′ of an ESDprotection device according to a third embodiment of the invention.

FIGS. 8A and 8B are top and sectional views along a line AA′ of an ESDprotection device according to a fourth embodiment of the invention.

FIGS. 9A and 9B are top and sectional views along a line AA′ of an ESDprotection device according to a fifth embodiment of the invention.

FIGS. 10A and 10B are top and sectional views along a line AA′ of an ESDprotection device according to a sixth embodiment of the invention.

FIGS. 11A and 11B are top and sectional views along a line AA′ of an ESDprotection device according to a seventh embodiment of the invention.

FIGS. 12A and 12B are top and sectional views along a line AA′ of an ESDprotection device according to an eighth embodiment of the invention.

FIGS. 13A and 13B are top and sectional views along a line AA′ of an ESDprotection device according to a ninth embodiment of the invention.

FIGS. 14A and 14B are top and sectional views along a line AA′ of an ESDprotection device according to a tenth embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

FIGS. 5A and 5B are top and sectional views along a line AA′ of an ESDprotection device according to a first embodiment of the invention. Itincludes a P silicon substrate 51, STI (shallow trench isolation) 52, aP guard ring 50 enclosing the STI 52, first gate 531, fourth gate 532,second gate 541, third gate 542, fifth gate 543, sixth gate 544 and Ndrain and source regions 551 and 552. The STI 52 is on the substrate 51and encloses an active region 56. The first gate 531 and fourth gate 532have two ends overlapping the STI 52 to stretch over the active region56, and are coupled to ground or a pre-driver. The second gate 541,third gate 542, fifth gate 543 and sixth gate 544 are disposed on acommon side and near each end of the first gate 531 and fourth gate 532.Each of the second gate 541, third gate 542, fifth gate 543 and sixthgate 544 has one end overlapping the STI 52. The first doping (drain)region 551 and second/third doping (source) region 552 are disposed inbetween and on outer sides of the first gate 531 and fourth gate 532,and coupled to second node 556 and first node 555, respectively. Morespecifically, the first node 555 is ground while the second node 556 isa pad. The first doping (drain) region 551 has first discontinuityregion 571, second discontinuity region 572, third discontinuity region573, and fourth discontinuity region 574, with source/drainimplantation, in the substrate under the second gate 541, third gate542, fifth gate 543 and sixth gate 544, respectively. The discontinuityregions 571˜574 are formed because the gates 541˜544 prevent thesubstrate under the gates 541˜544 from being doped during source/drainformation. Each of the first gate 531, fourth gate 532, second gate 541,third gate 542, fifth gate 543 and sixth gate 544 includes a conductinglayer 581 made of polysilicon, an oxide layer 582 made of silicon oxideunder the conducting layer 581 and spacers 583 made of silicon oxideadjacent to the conducting layer 581 and oxide layer 582.

In the first embodiment, the base width of the parasitic BJT is directlyrelated to the gate length of the NMOS and the longer channel transistorwill have a lower turned-on efficiency because of lower bipolarefficiency. The second gate 541, third gate 542, fifth gate 543 andsixth gate 544 at the AA′ region are used to increase the base width ofthe parasitic BJT at the AA′ region and decrease its turned-onefficiency. While the base width of the parasitic BJT at the BB′ regionis shorter than it is at the AA′ region, the turned-on efficiency of theBB′ region can be successfully balanced. Therefore, the parasitic BJT atthe BB′ region will turn on sooner than it will at the AA′ region,providing a larger bypass ESD current area than the AA′ region andincreasing the high MM ESD level. On the other hand, the HBM ESD levelwill not decrease while second gate 541, third gate 542, fifth gate 543and sixth gate 544 are inserted into the active region 56 under HBM ESDzapping because the bypass ESD current area is almost the same as thedevices of the prior arts.

Second Embodiment

FIGS. 6A and 6B are top and sectional views along a line AA′ of an ESDprotection device according to a second embodiment of the invention.With comparison to the ESD protection device shown in FIGS. 5A and 5B,it is noted that the second gate 541, third gate 542, fifth gate 543 andsixth gate 544 are disposed on the source region 552 so that the firstdiscontinuity region 571, second discontinuity region 572, thirddiscontinuity region 573, and fourth discontinuity region 574 arelocated in the source region 552 in the ESD protection device of FIGS.6A and 6B. The ESD protection devices in FIGS. 5A and 5B, and 6A and 6Bhave equal ESD performance.

Third Embodiment

FIGS. 7A and 7B are top and sectional views along a line AA′ of an ESDprotection device according to a third embodiment of the invention. Itincludes a P silicon substrate 71, STI (shallow trench isolation) 72, aP guard ring 70 enclosing the STI 72, first gate 731 and second gate732, and N drain 751 and source region 752. The STI 72 is on thesubstrate 71 and encloses an active region 76. The first gate 731 andsecond gate 732 have two ends overlapping the STI 72 to stretch over theactive region 76, and are coupled to ground or a pre-driver. The firstdoping (drain) region 751 and second/third doping (source) region 752are disposed in between and on outer sides of the first gate 731 andsecond gate 732, and coupled to second node 756 and first node 755,respectively. More specifically, the first node 755 is ground while thesecond node 756 is a pad. The first doping (drain) region 751 has firstcontinuity region 741, second continuity region 742, third continuityregion 743, and fourth continuity region 744 near each end of the firstgate 731 and second gate 732. The first continuity region continuityregion 741, second continuity region 742, third continuity region 743,and fourth continuity region 744 are formed by an implantation stepcompatible with a CMOS process, during which a mask blocks the firstdiscontinuity region 771, second discontinuity region 742, thirddiscontinuity region 743, and fourth discontinuity region 744 from N+ions. Each of the first gate 731 and second gate 732 includes aconducting layer 781 made of polysilicon, an oxide layer 782 made ofsilicon oxide under the conducting layer 781 and spacers 783 made ofsilicon oxide adjacent to the conducting layer 781 and oxide layer 782.

The layout method of the third embodiment, increases the AA′ regionresistance and decreases parasitic BJT turning on efficiency, making itpossible for ESD current to go through the BB′ region under MM ESDzapping. Thus, the MM ESD current bypasses bigger areas and has a higherMM ESD level than the device structures of prior arts. On the otherhand, the HBM ESD level will not decrease as it has no N+ diffusionbetween the gates and drain contact at the AA′ region. Moreover, theproposed layout method can also be applied to the PMOS to improve its MMESD robustness.

Fourth Embodiment

FIGS. 8A and 8B are top and sectional views along a line AA′ of an ESDprotection device according to a fourth embodiment of the invention.With comparison to the ESD protection device shown in FIGS. 7A and 7B,it is noted that the first discontinuity region 741, seconddiscontinuity region 742, third discontinuity region 743, and fourthdiscontinuity region 744 are located in the second doping (source)region 752. The ESD protection devices in FIGS. 7A and 7B, and 8A and 8Bhave equal ESD performance.

Fifth Embodiment

FIGS. 9A and 9B are top and sectional views along a line AA′ of an ESDprotection device according to a fifth embodiment of the invention. Itincludes a P silicon substrate 91, STI (shallow trench isolation) 92, aP guard ring 90 enclosing the STI 92, first gate 931 and second gate932, and N type first doping (drain) region 951 and second doping(source) region 952. The STI 92 is on the substrate 91 and encloses anactive region 96. The first gate 931 and second gate 932 have two endsoverlapping the STI 92 to stretch over the active region 96, and arecoupled to ground or a pre-driver. The first doping (drain) region 951and second/third doping (source) region 952 are disposed in between andon outer sides of the first gate 931 and second gate 932, and coupled tosecond node 956 and first node 955, respectively. More specifically, thefirst node 955 is ground while the second node 956 is a pad. Theisolation regions (STI regions) 941˜944 protrudes into the first doping(drain) region 951 near first and second ends of the first gate 931 andsecond gate 932. Each of the first gate 931 and second gate 932 includesa conducting layer 981 made of polysilicon, an oxide layer 982 made ofsilicon oxide under the conducting layer 981 and spacers 983 made ofsilicon oxide adjacent to the conducting layer 981 and oxide layer 982.

The layout method of the fifth embodiment, increases the AA′ regionresistances and decreases parasitic BJT turning on efficiency, making itpossible for ESD current to go through the BB′ region under MM ESDzapping. Thus, the MM ESD current bypasses bigger areas and has a higherMM ESD level than the device structures of prior arts. Conversely, theHBM ESD level will not decrease as STI is inserted between the gate anddrain contact at the AA′ region. Moreover, the proposed layout methodcan also be applied to the PMOS to improve ESD robustness.

Sixth Embodiment

FIGS. 10A and 10B are top and sectional views along a line AA′ of an ESDprotection device according to a sixth embodiment of the invention. Withcomparison to the ESD protection device shown in FIGS. 9A and 9B, it isnoted that the STI 941˜944 protrudes into the second/third doping(source) region 952. The ESD protection devices in FIGS. 9A and 9B, and10A and 10B have equal ESD performance.

Seventh Embodiment

FIGS. 11A and 11B are top and sectional views along a line AA′ of an ESDprotection device according to a seventh embodiment of the invention.For the sake of clarity, the same elements in FIGS. 11A and 11B, and 9Aand 9B refer to the same symbols. The ESD protection device includes a Psilicon substrate 91, STI (shallow trench isolation) 92, a P guard ring90 enclosing the STI 92, first gate 931 and second gate 932, and N typefirst doping (drain) region 951 and second doping (source) region 952.The STI 92 is on the substrate 91 and encloses an active region 96. Thegates 931 and 932 have two ends overlapping the STI 92 to stretch overthe active region 96, and are coupled to ground or a pre-driver. Thefirst doping (drain) region 951 and second/third doping (source) region952 are disposed in between and on outer sides of the first gate 931 andsecond gate 932, and coupled to second node 956 and first node 955,respectively. More specifically, the first node 955 is ground while thesecond node 956 is a pad. The STI 941˜944 has portions under the firstgate 931 and second gate 932 and near each end of the first gate 931 andsecond gate 932 protruding into both the first doping (drain) region 951and second/third doping (source) region 952. Each of the first gate 931and second gate 932 includes a conducting layer 981 made of polysilicon,an oxide layer 982 made of silicon oxide under the conducting layer 981and spacers 983 made of silicon oxide adjacent to the conducting layer981 and oxide layer 982.

The layout method of the fifth embodiment, increases the AA′ regionresistances and decreases parasitic BJT turning on efficiency, making itpossible for ESD current to go through the BB′ region under MM ESDzapping. Thus, the MM ESD current bypasses bigger areas and has a higherMM ESD level than the device structures of prior arts. Conversely, theHBM ESD level will not decrease as STI is inserted between the gate anddrain contact or below the gate at the AA′ region.

Eighth Embodiment

FIGS. 12A and 12B are top and sectional views along a line AA′ of an ESDprotection device according to an eighth embodiment of the invention.For the sake of clarity, the same elements in FIGS. 12A and 12B, and 5Aand 5B refer to the same symbols. The ESD protection device includes a Psilicon substrate 51, STI 52, a P guard ring 50 enclosing the STI 52,first gate 531 and second gate 532, N type first doping (drain) region551 and second doping (source) region 552, and third/fourth doping (ESDimplantation) regions 591 and 592. The STI 52 is on the substrate 51 andencloses an active region 56. The first gate 531 and second gate 532have two ends overlapping the STI 52 to stretch over the active region56, and are coupled to ground or a pre-driver. The first doping (drain)region 551 and second/fifth doping (source) region 552 are disposed inbetween and on outer sides of the first gate 531 and second gate 532,and coupled to a second node 556 and first node 555, respectively. Morespecifically, the first node 555 is ground while the second node 556 isa pad. The third doping (ESD implantation) regions 591 and 592 are Ntype lightly doped regions disposed under the first doping (drain)region 551 and second/fifth doping (source) region 552, and near eachend of the first gate 531 and second gate 532. The doping concentrationsof the third doping (ESD implantation) regions 591 and 592 are lowerthan those of the first doping (drain) region 551 and second/fifthdoping (source) region 552. Each of the first gate 531 and second gate532 includes a conducting layer 581 made of polysilicon, an oxide layer582 made of silicon oxide under the conducting layer 581 and spacers 583made of silicon oxide adjacent to the conducting layer 581 and oxidelayer 582.

In the eighth embodiment, the junction covered by the proposed ESDimplantation has an increased junction breakdown voltage, because it hasa lighter doping concentration across the p-n junction. The BB′ regionwithout covering the ESD implantation, however, has the originaljunction breakdown voltage, which is lower than the junction breakdownof the ESD implantation region. During the ESD stress, the junction ofthe BB′ region with the lowest junction breakdown voltage will be brokenfirst to discharge the ESD current. As previously mentioned, the AA′region provides a larger bypass area and path for ESD current and has ahigh MM ESD level. On the other hand, the HBM ESD level will notdecrease as the ESD implanted between the gate and drain contact at theAA′ region. This can also be applied to the PMOS to improve its ESDrobustness.

Ninth Embodiment

FIGS. 13A and 13B are top and sectional views along a line AA′ of an ESDprotection device according to an eighth embodiment of the invention.For the sake of clarity, the same elements in FIGS. 13A and 13B, and 5Aand 5B refer to the same symbols. The ESD protection device includes a Psilicon substrate 51, STI 52, a P type fourth doping region (guard ring)50 enclosing the STI 52, first gate 531 and second gate 532, N typefirst doping (drain) region 551 and second doping (source) region 552,and N type first doping region well 593 and second doping region well594. The STI 52 is on the substrate 51 and encloses an active region 56.The first gate 531 and second gate 532 have two ends overlapping the STI52 to stretch over the active region 56, and are coupled to ground or apre-driver. The first doping (drain) region 551 and second doping(source) region 552 are disposed in between and on outer sides of thefirst gate 531 and second gate 532, and coupled to a second node 556 andfirst node 555, respectively. More specifically, the first node 555 isground while the second node 556 is a pad. The N type first well 593 andsecond well 594 are disposed under the first doping (drain) region 551,and near first and second ends of the first gate 531 and second gate532. Each of the first gate 531 and second gate 532 includes aconducting layer 581 made of polysilicon, an oxide layer 582 made ofsilicon oxide under the conducting layer 581 and spacers 583 made ofsilicon oxide adjacent to the conducting layer 581 and oxide layer 582.

In the ninth embodiment, the MOSFET at the AA′ region has a lighterdoping concentration (N well) than that of the original (N+) drainjunction. Therefore, the junction covered by the proposed N well has anincreased junction breakdown voltage, because it has a lighter dopingconcentration across the p-n junction. However, the BB′ region withoutinserting N well has the original junction breakdown voltage, which islower than the junction breakdown of the AA′ region with N wellinserted. During the ESD stress, the junction the BB′ region with thelowest junction breakdown voltage will be broken first to discharge theESD current. As previously mentioned, the AA′ region provides a largerbypass area and path for ESD current and has a higher MM ESD level.

Tenth Embodiment

FIGS. 14A and 14B are top and sectional views along a line AA′ of an ESDprotection device according to an eighth embodiment of the invention.For the sake of clarity, the same elements in FIGS. 14A and 14B, and 5Aand 5B refer to the same symbols. The ESD protection device includes a Psilicon substrate 51, STI 52, a P guard ring 50 enclosing the STI 52,first gate 531 and second gate 532, and N type first doping (drain)region 551 and second doping (source) region 552. The STI 52 is on thesubstrate 51 and encloses an active region 56. The first gate 531 andsecond gate 532 have two ends overlapping the STI 52 to stretch over theactive region 56, and are coupled to ground or a pre-driver. The firstdoping (drain) region 551 and second/third doping (source) region 552are disposed in between and on outer sides of the first gates 531 andsecond gate 532, and coupled to a second node 556 and first node 555,respectively. More specifically, the first node 555 is ground while thesecond node 556 is a pad. The first gate 531 and second gate 532 arebent at an angle so that their center portions protrude into the firstdoping (drain) region 551. Thus, the widths of the first doping (drain)region 551 near the center portions of the first gate 531 and secondgate 532 are smaller than those near each end of the first gate 531 andsecond gate 532. Each of the first gate 531 and second gate 532 includesa conducting layer 581 made of polysilicon, an oxide layer 582 made ofsilicon oxide under the conducting layer 581 and spacers 583 made ofsilicon oxide adjacent to the conducting layer 581 and oxide layer 582.

In the tenth embodiment, at the AA′ region, the drain contact to thepoly edge space (DGS) is larger than the space at the BB′ region,therefore the equivalent base spacing of the parasitic BJT device at theAA′ region can be increased. With a wider base spacing, the BJT willhave a lower turn-on speed and lower current gain. In this structure,the turn-on efficiency of the parasitic BJT at the AA′ region decreases.ESD current will be discharged through the parasitic BJT at the BB′region under MM ESD zapping. Thus, the MM ESD current effectivelybypasses bigger areas and has a higher MM ESD level than the devicestructures of the prior arts. Conversely, the HBM ESD level will notdecrease and can also be applied to the PMOS to improve its ESDrobustness.

In all the previously described embodiments, the layouts are alsosuitable for PMOS although NMOS is used as an example. They are alsosuitable for stacked NMOS or PMOS in mixed voltage I/O circuits.

In conclusion, novel ESD protection device structures are proposed inthis invention for application under MM ESD stress in sub-quarter-micronCMOS technology. The ESD discharging current path in the NMOS or PMOSdevice structure is changed by the proposed new structures, thereforethe MM ESD level of the NMOS and PMOS can be significantly improved. Inthis invention, 6 kinds of new structures protect the lateral BJT at theAA′ region from current crowding and to balance the turned on efficiencyof the lateral BJT at the BB′ region. The MM ESD current bypassesthrough the lateral BJT at the BB′ region instead of the AA′ region, andhas a larger bypass area than the prior structures. The current crowdingproblem can be solved successfully, and have a higher MM ESD robustness.Moreover, these novel devices will not degrade the HBM ESD level and arewidely used in ESD protection circuits.

The foregoing description of the preferred embodiments of this inventionhas been presented for purposes of illustration and description. Obviousmodifications or variations are possible in light of the above teaching.The embodiments were chosen and described to provide the bestillustration of the principles of this invention and its practicalapplication to thereby enable those skilled in the art to utilize theinvention in various embodiments and with various modifications as aresuited to the particular use contemplated. All such modifications andvariations are within the scope of the present invention as determinedby the appended claims when interpreted in accordance with the breadthto which they are fairly, legally, and equitably entitled.

1. An ESD protection device comprising: a substrate; an isolation regionon the substrate, enclosing an active region; a first gate having afirst and second ends overlapping the isolation region to stretch overthe active region, and coupled to a first node; a first and seconddoping regions on the first and a second sides of the first gate, andcoupled to a second and the first nodes respectively; and a third dopingregion disposed under the first and second doping regions and near thefirst end of the first gate, having a doping concentration lower thanthat of the first and second doping regions.
 2. The ESD protectiondevice as claimed in claim 1, wherein the isolation region is a shallowtrench isolation.
 3. The ESD protection device as claimed in claim 1,wherein the first node is ground while the second node is a pad.
 4. TheESD protection device as claimed in claim 1 further comprising a fourthdoping region disposed under the first and second doping regions andnear the second end of the first gate, having a doping concentrationlower than that of the first and second doping regions.
 5. The ESDprotection device as claimed in claim 4 further comprising: a secondgate having a first and second end overlapping the isolation region tostretch over the active region, and coupled to the first node, whereinthe first doping region is on a first side of the second gate; and afifth doping region on a second side of the second gate, coupled to thesecond node; wherein the third doping region is disposed under thefirst, second and fifth doping regions and near the first end of thefirst and second gate while the fourth doping region is disposed underthe first, second and fifth doping regions and near the second end ofthe first and second gates.
 6. The ESD protection device as claimed inclaim 5, wherein each of the first and second gate comprises: aconducting layer; a gate oxide layer under the conducting layer; and afirst and second spacer respectively adjacent to two sides of theconducting layer and gate oxide layer.
 7. The ESD protection device asclaimed in claim 6, wherein the conducting layer is a polysilicon layerwhile the gate oxide layer, and the first and second spacer are siliconoxide layers.
 8. The ESD protection device as claimed in claim 1 furthercomprising a sixth doping region enclosing the isolation region.
 9. TheESD protection device as claimed in claim 8, wherein the substrate is aP substrate, the first, second, third, fourth and fifth doping regionare N doping regions, and the sixth doping region is a P doping region.10. An ESD protection device comprising: a substrate; an isolationregion on the substrate, enclosing an active region; a first gate havinga first and second ends overlapping the isolation region to stretch overthe active region, and coupled to a first node; a first and seconddoping regions on the first and a second sides of the first gate, andcoupled to a second and the first nodes respectively; and a first dopingregion well disposed under the first doping region and near the firstend of the first gate.
 11. The ESD protection device as claimed in claim10, wherein the isolation region is a shallow trench isolation.
 12. TheESD protection device as claimed in claim 10, wherein the first node isground while the second node is a pad.
 13. The ESD protection device asclaimed in claim 10 further comprising a second doping region welldisposed under the first doping region and near the second end of thefirst gate.
 14. The ESD protection device as claimed in claim 13 furthercomprising: a second gate having a first and second end overlapping theisolation region to stretch over the active region, and coupled to thefirst node, wherein the first doping region is on a first side of thesecond gate; and a third doping region on a second side of the secondgate, coupled to the second node.
 15. The ESD protection device asclaimed in claim 14, wherein each of the first and second gatescomprise: a conducting layer; a gate oxide layer under the conductinglayer; and a first and second spacer respectively adjacent to two sidesof the conducting layer and gate oxide layer.
 16. The ESD protectiondevice as claimed in claim 15, wherein the conducting layer is apolysilicon layer while the gate oxide layer, and the first and secondspacer are silicon oxide layers.
 17. The ESD protection device asclaimed in claim 10 further comprising a fourth doping region enclosingthe isolation region.
 18. The ESD protection device as claimed in claim16, wherein the substrate is a P substrate, the first, second and thirddoping regions are N doping regions, and the first and second dopingregions are P doping regions.
 19. An ESD protection device comprising: asubstrate; an isolation region on the substrate, enclosing an activeregion; a first gate having first and second ends overlapping theisolation region to stretch over the active region, and coupled to afirst node; first and second doping regions on the first and a secondsides of the first gate, and coupled to a second and the first nodesrespectively; and a third doping region disposed under the first dopingregion and near the first end of the first gate, having a dopingconcentration lower than that of the first and second doping regions.